Verilog Open Source Projects

Digital logic design tool and simulator

From the Transistor to the Web Browser, a rough outline for a 12 week course

A digital logic designer and circuit simulator.

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Chisel: A Modern Hardware Design Language

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Yosys Open SYnthesis Suite

Verilator open-source SystemVerilog simulator and lint system

Icarus Verilog

A FPGA friendly 32 bit RISC-V CPU implementation

Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cocotb: Python-based chip (RTL) verification

Open source FPGA-based NIC and platform for in-network compute

GPGPU microprocessor architecture

Circuit IR Compilers and Tools

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RTL, Cmodel, and testbench for NVDLA

Verilog AXI components for FPGA implementation

Scala based HDL

IC design and development should be faster，simpler and more reliable

Must-have verilog systemverilog modules

HDL libraries and projects

:snowflake: Visual editor for open FPGA boards

The Ultra-Low Power RISC-V Core

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

Verilog PCI express components

Haskell to VHDL/Verilog/SystemVerilog compiler

A Verilog synthesis flow for Minecraft redstone circuits

A small, light weight, RISC CPU soft core

XLS: Accelerated HW Synthesis

OpenXuantie - OpenC910 Core

Package manager and build abstraction tool for FPGA/ASIC development

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

An open source GPU based off of the AMD Southern Islands ISA.

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

32-bit Superscalar RISC-V CPU

The USRP™ Hardware Driver Repository

Verilog to Routing -- Open Source CAD Flow for FPGA Research

A repository of gate-level simulators and tools for the original Game Boy.

Hardware Description Languages

Generator Bootcamp Material: Learn Chisel the Right Way

All in one vscode plugin for HDL development

Bluespec Compiler (BSC)

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

An Open-source FPGA IP Generator

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

SystemVerilog compiler and language services

Hardcaml is an OCaml library for designing hardware.

3-stage RV32IMACZb* processor with debug

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

:seedling: Open source ecosystem for open FPGA boards

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Veryl: A Modern Hardware Description Language

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。