Riscv Open Source Projects

A simple and easy-to-use library to enjoy videogames programming

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Xv6 for RISC-V

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

Tengine is a lite, high performance, modular inference engine for embedded device

Rocket Chip Generator

Rust version of THU uCore OS. Linux compatible.

A FPGA friendly 32 bit RISC-V CPU implementation

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A collaborative list of awesome Zig libraries and resources.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Unix-like OS in Rust inspired by xv6-riscv

RARS -- RISC-V Assembler and Runtime Simulator

A very simple and easy to understand RISC-V core.

A self-hosting and educational C optimizing compiler

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see prototyper folder.

The RISC-V Virtual Machine

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

Working draft of the proposed RISC-V V vector extension

C++20 RISC-V RV32/64/128 userspace emulator library

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

3-stage RV32IMACZb* processor with debug

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

A Tool to make Build and Run eBPF programs easier

RISC-V simulator for x86-64

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

RISC-V processor emulator written in Rust+WASM

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

EDK II sample platform branches and tags

Simple RISC-V 3-stage Pipeline in Chisel

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Compact and Efficient RISC-V RV32I[MAFC] emulator

Small & portable byte-aligned LZ77 compression

An unofficial assembly reference for RISC-V.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Fork of OpenOCD that has RISC-V support

RISC-V Debug Specification Standard

Build a minimal multi-tasking OS kernel for RISC-V from scratch

A collection of some awesome public FPGA projects.

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

RISC-V Assembler and Runtime Simulator

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development board. 本项目旨在真正从0开始构建嵌入式linux系统，为了剖析芯片从上电开始执行第一条指令到整个系统运行，基于qemu定制模拟器开发板。

OpenEmbedded/Yocto layer for RISC-V Architecture

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Unicorn Emulator Debug Server - Written in Rust, with bindings for C, Go, Java and Python

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

CKB's vm, based on open source RISC-V ISA

A curated list of open-source projects that help exploit Intel SGX technology